An End-to-End Workflow to Efficiently Compress and Deploy DNN Classifiers On SoC/FPGA

Abstract

Machine learning models have demonstrated discriminativeand representative learning capabilities over a widerange of applications, even at the cost of high computationalcomplexity. Due to their parallel processing capabilities, reconfigurability,and low power consumption, Systems on Chip basedon a Field Programmable Gate Array (SoC/FPGA) have beenused to face this challenge. Nevertheless, SoC/FPGA devicesare resource-constrained, which implies the need for optimaluse of technology for the computation and storage operationsinvolved in ML-based inference. Consequently, mapping a DeepNeural Network (DNN) architecture to a SoC/FPGA requirescompression strategies to obtain a hardware design with agood compromise between effectiveness, memory footprint, andinference time. This paper presents an efficient end-to-endworkflow for deploying DNNs on an SoC/FPGA by integratinghyperparameter tuning through Bayesian optimization with anensemble of compression techniques.