Multilevel Current-Source Inverter With FPGA Control | ||
| dc.conicet.fuente | unificacion | |
| dc.conicet.organizacion | Instituto Tecnológico de Buenos Aires | |
| dc.conicet.organizacion | Instituto Tecnológico de Buenos Aires | |
| dc.conicet.organizacion | Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata | |
| dc.conicet.organizacion | Universidad Nacional de La Plata. Facultad de Ingeniería | |
| dc.conicet.paisOrganizacion | Argentina | |
| dc.conicet.paisOrganizacion | Argentina | |
| dc.conicet.paisOrganizacion | Argentina | |
| dc.conicet.paisOrganizacion | Argentina | |
| dc.conicet.produccionid | 7856030 | |
| dc.contributor.author | Aguirre, Miguel Pablo | |
| dc.contributor.author | Calvino, Laura | |
| dc.contributor.author | Valla, Maria Ines | |
| dc.date.accessioned | 2019-05-20T21:21:12Z | |
| dc.date.available | 2019-05-20T21:21:12Z | |
| dc.date.issued | 2013-01 | |
| dc.date.updated | 2019-05-14T21:07:16Z | |
| dc.description.abstract | In this paper, a multilevel current-source inverter (MCSI) topology is analyzed. The issue of constructing a novel modular single-rating inductor MCSI is explored, taking advantage of the features of field-programmable gate arrays (FPGA) for control and gate signal generation. The proposed topology is built with identical modules where all inductors carry the same amount of current, simplifying the construction and operation of industrial applications with higher efficiency. A new state-machine approach, which is easy to implement in an FPGA, and a proper implementation of the phase-shifted carrier sinusoidal pulse width modulation (PSC-SPWM) allow both current balance in all modules and effective switching-frequency minimization. The performance of the MSCI proposed is simulated with Matlab and is verified by constructing a prototype. | es |
| dc.description.fil | Fil: Aguirre, Miguel Pablo. Instituto Tecnológico de Buenos Aires; Argentina | |
| dc.description.fil | Fil: Calvino, Laura. Instituto Tecnológico de Buenos Aires; Argentina | |
| dc.description.fil | Fil: Valla, Maria Ines. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata; Argentina. Universidad Nacional de La Plata. Facultad de Ingeniería; Argentina | |
| dc.format | application/pdf | es |
| dc.identifier.citation | Aguirre, Miguel Pablo; Calvino, Laura; Valla, Maria Ines; Multilevel Current-Source Inverter With FPGA Control; Institute of Electrical and Electronics Engineers; Ieee Transactions On Industrial Electronics; 60; 1; 1-2013; 3-10 | es |
| dc.identifier.eissn | 1557-9948 | es |
| dc.identifier.institucional | CONICET | |
| dc.identifier.issn | 0278-0046 | es |
| dc.identifier.repo | CONICET Digital | |
| dc.identifier.uri | http://hdl.handle.net/11336/76757 | |
| dc.journal.ciudad | Nueva York | es |
| dc.journal.number | 1 | es |
| dc.journal.pagination | 3-10 | es |
| dc.journal.pais | Estados Unidos | es |
| dc.journal.title | Ieee Transactions On Industrial Electronics | es |
| dc.journal.volume | 60 | es |
| dc.language.iso | eng | es |
| dc.publisher | Institute of Electrical and Electronics Engineers | es |
| dc.relation.alternativeid | info:eu-repo/semantics/altIdentifier/url/http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6138305 | |
| dc.relation.alternativeid | info:eu-repo/semantics/altIdentifier/doi/http://dx.doi.org/10.1109/TIE.2012.2185014 | |
| dc.rights | info:eu-repo/semantics/openAccess | * |
| dc.rights.uri | https://creativecommons.org/licenses/by-nc-sa/2.5/ar/ | * |
| dc.subject | Field-Programmable Gate Array (Fpga) | es |
| dc.subject | Multilevel Current-Source Inverter (Mcsi) | es |
| dc.subject | Phase-Shifted Carrier Spwm (Psc-Spwm) | es |
| dc.subject.classification | Ingeniería de Sistemas y Comunicaciones | es |
| dc.subject.classification | Ingeniería Eléctrica, Ingeniería Electrónica e Ingeniería de la Información | es |
| dc.subject.classification | INGENIERÍAS Y TECNOLOGÍAS | es |
| dc.title | Multilevel Current-Source Inverter With FPGA Control | es |
| dc.type | info:eu-repo/semantics/article | |
| dc.type | info:ar-repo/semantics/artículo | |
| dc.type | info:eu-repo/semantics/publishedVersion | |
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