Heterogeneous Capacitor‐less Two‐transistor Dynamic Random Access Memory Cell with Long Retention Time and High Sensing Current Supporting 5‐Bit Multilevel Operation

Abstract

A heterogeneous capacitor-less two-transistor (2T0C) dynamic random accessmemory (DRAM) cell is fabricated, featuring a write transistor with an amorphousindium–gallium–zinc–oxide (a-IGZO) channel and a read transistor with asingle crystal silicon (Si) channel. These transistors are vertically integrated toachieve high integration density. A data retention time of over 4800 s is achieveddue to the wide bandgap of a-IGZO, and a high sensing current of over166 μA μm1 is achieved due to the high mobility of the Si. This high sensingcurrent allows for a short read latency of 1.34 ns and 5-bit multilevel celloperation, the highest reported for 2T0C DRAM cells.