Design and evaluation of an All-Digital programmable delay Line in 130-nm CMOS

Abstract

Programmable delay lines are often used to provide precise transition timing control in very-large-scale integration (VLSI) systems. In this work, a digitally controlled delay line that achieves a resolution step of 340 ps and a maximum delay of 50 ns is proposed. The delay element has a linear delay characteristic and calibration capabilities in a range of 20% using a mixed model of current starving and load switching strategy. Experimental results of the circuit implementation in a 130-nm CMOS process are presented.