Cache sharing administration for performance fairness using D3C miss classification in chip multi-processors

Abstract

This work presents a study of fairness in cache sharing be-tween processes in a chip multiprocessor (CMP). We propose a new algorithm that uses a metric based on the D3C miss classication and LRUStack Distance, to measure the fairness in the administration of the resources to achieve an increase of the global IPC of all executed processes.Shared cache miss rate, IPC and bandwidth metrics were considered toanalyze the simulation results obtained using three test sets. The obtained results showed that the proposed dynamic management policycompared to Capitalist management policy, has a lower global miss ratein shared cache and lower bandwidth usage for each test set studied andfullls its objective of managing the shared cache space for every processwhile improving the overall IPC.