Embedded wireless delay tolerant networks on chips for segmented architectures

Abstract

Fault-tolerant systems were traditionally based on the use of local redundancies. But currently, network technologies have allowed the emergence of novel distributed alternatives. Among these, disruption tolerant networks (DTNs) are designed to be robust against all sorts of delays and disruptions. DTNs were initially applied in scenarios with long distances and variable interruption intervals between their nodes. Wireless delay tolerant networks on chips (WDTNOCs) have been recently introduced as an enabling technology that can inherit some DTNs characteristics while improving embedded systems dependability. This work presents new results regarding ´hop counts´ and ´end to end delays´ for linear-shaped WDTNOCs under parametric transient fault scenarios. Extensive simulation results demonstrate that it is also possible to improve system´s performance and graceful degradation characteristics. Feasibility aspects regarding the required buffer sizes are also addressed. Finally, as an important application possibility, it is shown how the so-called segmented architectures can directly benefit from embedded WDTNOCs.