Artículo

Post-silicon Validation Procedure for a PWL ASIC Microprocessor Architecture

Lifschitz, Omar D.; Rodriguez, Juan AgustinIcon ; Julian, Pedro MarceloIcon ; Agamennoni, Osvaldo Enrique
Fecha de publicación: 07/2011
Editorial: Institute of Electrical and Electronics Engineers
Revista: IEEE Latin America Transactions
ISSN: 1548-0992
Idioma: Inglés
Tipo de recurso: Artículo publicado
Clasificación temática:

Resumen

In this paper, we present the environment set for validation and testing a particular ASIC that implements a piecewise linear (PWL) architecture. Description for a package debug propose is included. Methodologies for power consumption and maximum operation frequency estimation, based on laboratory measurements, are described.
Palabras clave: Piece Wise Linear , ASIC , Nonlinear Systems
 
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info:eu-repo/semantics/openAccess Excepto donde se diga explícitamente, este item se publica bajo la siguiente descripción: Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Unported (CC BY-NC-SA 2.5)
Identificadores
URI: http://hdl.handle.net/11336/102526
URL: https://ieeexplore.ieee.org/document/5993733
DOI: https://doi.org/10.1109/TLA.2011.5993733
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Articulos(IIIE)
Articulos de INST.DE INVEST.EN ING.ELECTRICA "A.DESAGES"
Citación
Lifschitz, Omar D.; Rodriguez, Juan Agustin; Julian, Pedro Marcelo; Agamennoni, Osvaldo Enrique; Post-silicon Validation Procedure for a PWL ASIC Microprocessor Architecture; Institute of Electrical and Electronics Engineers; IEEE Latin America Transactions; 9; 4; 7-2011; 492-497
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