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dc.contributor.author
de Giusti, Laura Cristina  
dc.contributor.author
Chichizola, Franco  
dc.contributor.author
Naiouf, Ricardo Marcelo  
dc.contributor.author
Ripoll, Ana  
dc.contributor.author
de Giusti, Armando Eduardo  
dc.date.available
2024-08-06T14:16:00Z  
dc.date.issued
2007-12  
dc.identifier.citation
de Giusti, Laura Cristina; Chichizola, Franco; Naiouf, Ricardo Marcelo; Ripoll, Ana; de Giusti, Armando Eduardo; A model for the automatic mapping of tasks to processors in heterogeneous multi-cluster architectures; Universidad Nacional de La Plata. Facultad de Informática; Journal of Computer Science and Technology; 7; 1; 12-2007; 39-44  
dc.identifier.issn
1666-6046  
dc.identifier.uri
http://hdl.handle.net/11336/241894  
dc.description.abstract
This paper discusses automatic mapping methods for concurrent tasks to processors applying graph analysis for the relation among tasks, in which processing and communicating times are incorporated.Starting by an analysis in which processors are homogeneous and data transmission times do not depend on the processors that are communicating (a typical case in homogeneous clusters), we progress to extend the model to heterogeneous processors having the possibility of different communication levels, applicable to a multicluster.Some results obtained with the model and future work lines are presented, particularly, the possibility of obtaining the required optimal number of processors, keeping a constant efficiency level.  
dc.format
application/pdf  
dc.language.iso
eng  
dc.publisher
Universidad Nacional de La Plata. Facultad de Informática  
dc.rights
info:eu-repo/semantics/openAccess  
dc.rights.uri
https://creativecommons.org/licenses/by-nc/2.5/ar/  
dc.subject
Parallel Systems  
dc.subject
Cluster and Multi-Cluster Architectures  
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Performance Prediction Models  
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Mapping of Tasks to Processors  
dc.subject
Homogeneous and Heterogeneous Processors  
dc.subject.classification
Ingeniería de Sistemas y Comunicaciones  
dc.subject.classification
Ingeniería Eléctrica, Ingeniería Electrónica e Ingeniería de la Información  
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INGENIERÍAS Y TECNOLOGÍAS  
dc.title
A model for the automatic mapping of tasks to processors in heterogeneous multi-cluster architectures  
dc.type
info:eu-repo/semantics/article  
dc.type
info:ar-repo/semantics/artículo  
dc.type
info:eu-repo/semantics/publishedVersion  
dc.date.updated
2024-08-05T13:39:28Z  
dc.journal.volume
7  
dc.journal.number
1  
dc.journal.pagination
39-44  
dc.journal.pais
Estados Unidos  
dc.journal.ciudad
Albuquerque  
dc.description.fil
Fil: de Giusti, Laura Cristina. Universidad Nacional de La Plata. Facultad de Informática. Instituto de Investigación en Informática Lidi; Argentina  
dc.description.fil
Fil: Chichizola, Franco. Universidad Nacional de La Plata. Facultad de Informática. Instituto de Investigación en Informática Lidi; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata; Argentina  
dc.description.fil
Fil: Naiouf, Ricardo Marcelo. Universidad Nacional de La Plata. Facultad de Informática. Instituto de Investigación en Informática Lidi; Argentina  
dc.description.fil
Fil: Ripoll, Ana. Universidad de Barcelona; España  
dc.description.fil
Fil: de Giusti, Armando Eduardo. Universidad Nacional de La Plata. Facultad de Informática. Instituto de Investigación en Informática Lidi; Argentina  
dc.journal.title
Journal of Computer Science and Technology  
dc.relation.alternativeid
info:eu-repo/semantics/altIdentifier/url/https://www.redalyc.org/articulo.oa?id=638067340019  
dc.relation.alternativeid
info:eu-repo/semantics/altIdentifier/url/https://journal.info.unlp.edu.ar/JCST/article/view/801