Evento

A PWL ASIC design for maximum throughput

Lifschitz, Omar D.; Julian, Pedro MarceloIcon ; Agamennoni, Osvaldo Enrique
Tipo del evento: Congreso
Nombre del evento: 7th Argentine School of Micro-Nanoelectronics, Technology and Applications
Fecha del evento: 15/08/2013
Institución Organizadora: Universidad Tecnológica Nacional; Institute of Electrical and Electronics Engineers;
Título del Libro: 2013 7th Argentine School of Micro-Nanoelectronics, Technology and Applications
Editorial: Institute of Electrical and Electronics Engineers
ISBN: 978-9-8719-0744-1
Idioma: Inglés
Clasificación temática:

Resumen

This paper presents the design of a digital architecture for a Simplicial piecewise linear (PWL) integrated circuit (IC). This design maximizes the IC throughput by using an enhanced pipeline architecture and taking advantage of the maximum memory device performance.
Palabras clave: Digital architecture , PWL , NOE
 
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info:eu-repo/semantics/openAccess Excepto donde se diga explícitamente, este item se publica bajo la siguiente descripción: Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Unported (CC BY-NC-SA 2.5)
Identificadores
URI: http://hdl.handle.net/11336/238689
URL: http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6602018
Colecciones
Eventos(IIIE)
Eventos de INST.DE INVEST.EN ING.ELECTRICA "A.DESAGES"
Citación
A PWL ASIC design for maximum throughput; 7th Argentine School of Micro-Nanoelectronics, Technology and Applications; Buenos Aires; Argentina; 2013; 92-95
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