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dc.contributor.author
Molina, Romina
dc.contributor.author
Gil Costa, Graciela Verónica
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dc.contributor.author
Crespo, Maria Liz
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dc.contributor.author
Ramponi, Giovanni
dc.date.available
2023-10-10T17:32:57Z
dc.date.issued
2022-09
dc.identifier.citation
Molina, Romina; Gil Costa, Graciela Verónica; Crespo, Maria Liz; Ramponi, Giovanni; High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks; Institute of Electrical and Electronics Engineers; IEEE Access; 10; 9-2022; 90429-90455
dc.identifier.issn
2169-3536
dc.identifier.uri
http://hdl.handle.net/11336/214735
dc.description.abstract
Hardware accelerators based on field programmable gate array (FPGA) and system on chip (SoC) devices have gained attention in recent years. One of the main reasons is that these devices contain reconfigurable logic, which makes them feasible for boosting the performance of applications. High-level synthesis (HLS) tools facilitate the creation of FPGA code from a high level of abstraction using different directives to obtain an optimized hardware design based on performance metrics. However, the complexity of the design space depends on different factors such as the number of directives used in the source code, the available resources in the device, and the clock frequency. Design space exploration (DSE) techniques comprise the evaluation of multiple implementations with different combinations of directives to obtain a design with a good compromise between different metrics. This paper presents a survey of models, methodologies, and frameworks proposed for metric estimation, FPGA-based DSE, and power consumption estimation on FPGA/SoC. The main features, limitations, and trade-offs of these approaches are described. We also present the integration of existing models and frameworks in diverse research areas and identify the different challenges to be addressed.
dc.format
application/pdf
dc.language.iso
eng
dc.publisher
Institute of Electrical and Electronics Engineers
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dc.rights
info:eu-repo/semantics/restrictedAccess
dc.rights.uri
https://creativecommons.org/licenses/by-nc-sa/2.5/ar/
dc.subject
COMPUTING MODELS
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DESIGN SPACE EXPLORATION
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FIELD PROGRAMMABLE GATE ARRAY (FPGA)
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POWER CONSUMPTION
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SYSTEM ON CHIP (SOC)
dc.subject.classification
Ciencias de la Computación
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dc.subject.classification
Ciencias de la Computación e Información
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CIENCIAS NATURALES Y EXACTAS
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dc.title
High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks
dc.type
info:eu-repo/semantics/article
dc.type
info:ar-repo/semantics/artículo
dc.type
info:eu-repo/semantics/publishedVersion
dc.date.updated
2023-10-10T13:08:30Z
dc.journal.volume
10
dc.journal.pagination
90429-90455
dc.journal.pais
Estados Unidos
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dc.description.fil
Fil: Molina, Romina. Universidad Nacional de San Luis; Argentina
dc.description.fil
Fil: Gil Costa, Graciela Verónica. Universidad Nacional de San Luis; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - San Luis; Argentina
dc.description.fil
Fil: Crespo, Maria Liz. The Abdus Salam; Italia. The Abdus Salam. International Centre for Theoretical Physics; Italia
dc.description.fil
Fil: Ramponi, Giovanni. Università degli Studi di Trieste; Italia
dc.journal.title
IEEE Access
dc.relation.alternativeid
info:eu-repo/semantics/altIdentifier/doi/http://dx.doi.org/10.1109/ACCESS.2022.3201107
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