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dc.contributor.author
Arnone, Leonardo Jose  
dc.contributor.author
Castiñeira Moreira, Jorge  
dc.contributor.author
Farrell, P. G.  
dc.date.available
2023-09-21T23:35:08Z  
dc.date.issued
2012-08  
dc.identifier.citation
Arnone, Leonardo Jose; Castiñeira Moreira, Jorge; Farrell, P. G.; Field programmable gate arrays implementations of low complexity soft-input soft-output low-density parity-check decoders; Institution of Engineering and Technology; Iet Communications; 6; 12; 8-2012; 1670-1675  
dc.identifier.issn
1751-8628  
dc.identifier.uri
http://hdl.handle.net/11336/212607  
dc.description.abstract
Low-density parity-check (LDPC) codes are very efficient error control codes that are being considered for use in many next-generation communication systems. In this study low complexity soft-input, soft-output (SISO) field programmable gate arrays (FPGA) implementations of a novel logarithmic sum-product (LogSP) iterative LDPC decoder and a recently proposed simplified soft Euclidean distance (SSD) iterative LDPC decoder are presented, and their complexities and performance are compared. These implementations operate over any choice of parity check matrix (including those randomly generated, structurally generated and either systematic or non-systematic) and can be parametrically adapted for any code rate. The proposed implementations are both of very low complexity, because they operate using only sums, subtractions, comparisons and look-up tables, which makes them particularly suitable for FPGA realisation. The SSD decoder has a lower implementation complexity than the LogSP LDPC decoder and it also offers the advantage of not requiring knowledge of the channel signal-to-noise ratio, unlike most other LDPC decoders.  
dc.format
application/pdf  
dc.language.iso
eng  
dc.publisher
Institution of Engineering and Technology  
dc.rights
info:eu-repo/semantics/openAccess  
dc.rights.uri
https://creativecommons.org/licenses/by-nc-sa/2.5/ar/  
dc.subject
FPGA IMPLEMENTATION  
dc.subject
EUCLIDEAN METRIC  
dc.subject
LDPC CODES  
dc.subject.classification
Telecomunicaciones  
dc.subject.classification
Ingeniería Eléctrica, Ingeniería Electrónica e Ingeniería de la Información  
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INGENIERÍAS Y TECNOLOGÍAS  
dc.title
Field programmable gate arrays implementations of low complexity soft-input soft-output low-density parity-check decoders  
dc.type
info:eu-repo/semantics/article  
dc.type
info:ar-repo/semantics/artículo  
dc.type
info:eu-repo/semantics/publishedVersion  
dc.date.updated
2023-05-08T17:29:07Z  
dc.journal.volume
6  
dc.journal.number
12  
dc.journal.pagination
1670-1675  
dc.journal.pais
Reino Unido  
dc.description.fil
Fil: Arnone, Leonardo Jose. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Departamento de Ingeniería Eléctrica; Argentina  
dc.description.fil
Fil: Castiñeira Moreira, Jorge. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Departamento de Ingeniería Eléctrica; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Mar del Plata; Argentina  
dc.description.fil
Fil: Farrell, P. G.. Lancaster University; Reino Unido  
dc.journal.title
Iet Communications  
dc.relation.alternativeid
info:eu-repo/semantics/altIdentifier/url/https://digital-library.theiet.org/content/journals/10.1049/iet-com.2011.0767  
dc.relation.alternativeid
info:eu-repo/semantics/altIdentifier/doi/https://doi.org/10.1049/iet-com.2011.0767