Artículo
A high-efficiency isolated PFC AC-DC topology with reduced number of semiconductor devices
Fecha de publicación:
08/2022
Editorial:
Institute of Electrical and Electronics Engineers Inc.
Revista:
IEEE Journal of Emerging and Selected Topics in Power Electronics
ISSN:
2168-6777
e-ISSN:
2168-6785
Idioma:
Inglés
Tipo de recurso:
Artículo publicado
Clasificación temática:
Resumen
A new three-level isolated ac-dc power factor correction (PFC) topology with a minimum number of semiconductor devices is the focus of this article. This topology provides a high input power factor (PF), soft-switching, and higher efficiency than existing isolated ac-dc converters. Furthermore, the proposed circuit has lower voltage rating requirements for the secondary side devices, which leads to a lower total cost and minimizes total converter losses. This article presents a theoretical analysis describing the complete characterization of this new topology, and experimental results on a 1-kW prototype showing high PF and efficiency throughout the operating range.
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Articulos (IITEMA)
Articulos de INSTITUTO DE INVESTIGACIONES EN TECNOLOGIAS ENERGETICAS Y MATERIALES AVANZADOS
Articulos de INSTITUTO DE INVESTIGACIONES EN TECNOLOGIAS ENERGETICAS Y MATERIALES AVANZADOS
Citación
Aldosari, Obaid; Rodriguez, Luciano Andres Garcia; Oggier, German Gustavo; Balda, Juan Carlos; A high-efficiency isolated PFC AC-DC topology with reduced number of semiconductor devices; Institute of Electrical and Electronics Engineers Inc.; IEEE Journal of Emerging and Selected Topics in Power Electronics; 10; 4; 8-2022; 3631-3642
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