Mostrar el registro sencillo del ítem
dc.contributor.author
Assayad, Ismail
dc.contributor.author
Yovine, Sergio Fabian
dc.date.available
2017-05-12T15:55:46Z
dc.date.issued
2010-06
dc.identifier.citation
Assayad, Ismail; Yovine, Sergio Fabian; A scheduler synthesis methodology for joint SW/HW design exploration of SoC; Springer; Design Automation For Embedded Systems; 14; 2; 6-2010; 75-103
dc.identifier.issn
0929-5585
dc.identifier.uri
http://hdl.handle.net/11336/16379
dc.description.abstract
The introduction of high-performance applications such as multimedia applications into SoCs led the manufacturers to provide embedded SoCs able to offer an important computing power which makes it possible to answer the increasing requirements of future evolutions of these applications. One of the adopted solutions is the use of multiprocessor SoCs. In this paper, we present a joint SW/HW design exploration methodology for multiprocessor SoCs. The system model relies on transaction-level component-based models for modeling parallel software and multiprocessor hardware. Our proposal comprises two original points. First, we propose a composable software-level scheduler constraints synthesis technique. Second, we present a combined software-level and exploratory hardware-level schedulers. The methodology has the advantage of combining real-time requirements of software with effective exploitation of multiprocessor hardware. We describe and apply the methodology to synthesize a scheduler of a slice-based MPEG-4 video encoder on the multiprocessor Cake SoCs.
dc.format
application/pdf
dc.language.iso
eng
dc.publisher
Springer
dc.rights
info:eu-repo/semantics/restrictedAccess
dc.rights.uri
https://creativecommons.org/licenses/by-nc-sa/2.5/ar/
dc.subject
Multiprocessor System-On-Chips (Socs)
dc.subject
Sw/Hw Design
dc.subject
Scheduling - Exploration
dc.subject
Real-Time Requirements
dc.subject.classification
Ciencias de la Computación
dc.subject.classification
Ciencias de la Computación e Información
dc.subject.classification
CIENCIAS NATURALES Y EXACTAS
dc.title
A scheduler synthesis methodology for joint SW/HW design exploration of SoC
dc.type
info:eu-repo/semantics/article
dc.type
info:ar-repo/semantics/artículo
dc.type
info:eu-repo/semantics/publishedVersion
dc.date.updated
2017-05-11T20:58:32Z
dc.identifier.eissn
1572-8080
dc.journal.volume
14
dc.journal.number
2
dc.journal.pagination
75-103
dc.journal.pais
Estados Unidos
dc.description.fil
Fil: Assayad, Ismail. University of Hassan II Ain Chock; Marruecos
dc.description.fil
Fil: Yovine, Sergio Fabian. Universidad de Buenos Aires. Facultad de Ciencias Exactas y Naturales. Departamento de Computación; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentina
dc.journal.title
Design Automation For Embedded Systems
dc.relation.alternativeid
info:eu-repo/semantics/altIdentifier/doi/http://dx.doi.org/10.1007/s10617-010-9051-5
dc.relation.alternativeid
info:eu-repo/semantics/altIdentifier/url/https://link.springer.com/article/10.1007%2Fs10617-010-9051-5
Archivos asociados