A Shared Way Set Associative On-Chip Cache

Abstract

A new cache memory organization called “Shared-Way Set Associative” (SWSA) is described in this paper. It consists of a modified two-way set associative scheme in which one way is larger than the other. We show how better use of memory is obtained, without the costs that higher-associativities have. An expression for calculating the non-integer degree of associativity of SWSA caches is given. Several replacement policies are discussed. Miss rate statistics for the SPEC95 and additional benchmarks are presented for first and second level SWSA caches, together with a detailed analysis of conflicts using the D3C classification of misses. For large caches the miss rates of SWSA caches are similar to those 33 percent larger two-way set associative caches. The issue of hardware implementation is addressed, and we explain why SWSA caches may have advantages, especially with configurations with very unbalanced ways which have miss rates that are very similar to those of slightly smaller two-way caches. We conclude that shared-way set associativity shows benefits compared to two-way set associativity, and may also be favorably compared with direct-mapping and even to higher associativities depending on other architectural and technological issues.