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dc.contributor.author
Hamkalo, Jose Luis
dc.contributor.author
Cernuschi Frias, Bruno
dc.contributor.author
Djordjalian,Andrés
dc.date.available
2020-07-24T15:10:53Z
dc.date.issued
2004-12
dc.identifier.citation
Hamkalo, Jose Luis; Cernuschi Frias, Bruno; Djordjalian,Andrés; A Shared Way Set Associative On-Chip Cache; International Society for Computers and Their Applications; International Journal of Computers and Their Applications; 11; 4; 12-2004; 224-233
dc.identifier.issn
1076-5204
dc.identifier.uri
http://hdl.handle.net/11336/110175
dc.description.abstract
A new cache memory organization called “Shared-Way Set Associative” (SWSA) is described in this paper. It consists of a modified two-way set associative scheme in which one way is larger than the other. We show how better use of memory is obtained, without the costs that higher-associativities have. An expression for calculating the non-integer degree of associativity of SWSA caches is given. Several replacement policies are discussed. Miss rate statistics for the SPEC95 and additional benchmarks are presented for first and second level SWSA caches, together with a detailed analysis of conflicts using the D3C classification of misses. For large caches the miss rates of SWSA caches are similar to those 33 percent larger two-way set associative caches. The issue of hardware implementation is addressed, and we explain why SWSA caches may have advantages, especially with configurations with very unbalanced ways which have miss rates that are very similar to those of slightly smaller two-way caches. We conclude that shared-way set associativity shows benefits compared to two-way set associativity, and may also be favorably compared with direct-mapping and even to higher associativities depending on other architectural and technological issues.
dc.format
application/pdf
dc.language.iso
eng
dc.publisher
International Society for Computers and Their Applications
dc.rights
info:eu-repo/semantics/openAccess
dc.rights.uri
https://creativecommons.org/licenses/by-nc-sa/2.5/ar/
dc.subject
CACHE MEMORY
dc.subject
ASSOCIATIVITY
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REPLACEMENT POLICY
dc.subject.classification
Hardware y Arquitectura de Computadoras
dc.subject.classification
Ingeniería Eléctrica, Ingeniería Electrónica e Ingeniería de la Información
dc.subject.classification
INGENIERÍAS Y TECNOLOGÍAS
dc.title
A Shared Way Set Associative On-Chip Cache
dc.type
info:eu-repo/semantics/article
dc.type
info:ar-repo/semantics/artículo
dc.type
info:eu-repo/semantics/publishedVersion
dc.date.updated
2020-05-11T19:02:47Z
dc.journal.volume
11
dc.journal.number
4
dc.journal.pagination
224-233
dc.journal.pais
Estados Unidos
dc.description.fil
Fil: Hamkalo, Jose Luis. Universidad de Buenos Aires. Facultad de Ingeniería; Argentina
dc.description.fil
Fil: Cernuschi Frias, Bruno. Universidad de Buenos Aires. Facultad de Ingeniería; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas. Oficina de Coordinación Administrativa Saavedra 15. Instituto Argentino de Matemática Alberto Calderón; Argentina
dc.description.fil
Fil: Djordjalian,Andrés. Universidad de Buenos Aires. Facultad de Ingeniería; Argentina
dc.journal.title
International Journal of Computers and Their Applications
dc.relation.alternativeid
info:eu-repo/semantics/altIdentifier/url/http://www-personal.umd.umich.edu/~qzhu/cisdb/ijca/journal.htm
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