Evento

Implementation of a High-Resolution Symmetric PWM Based on Custom CMOS Delay Lines

Morales, Juan IgnacioIcon ; Chierchie, FernandoIcon ; Mandolesi, Pablo Sergio; Paolini, Eduardo Emilio
Tipo del evento: Workshop
Nombre del evento: XVIII Workshop on Information Processing and Control
Fecha del evento: 18/09/2019
Institución Organizadora: Universidad Nacional del Sur;
Título del Libro: XVIII Workshop on Information Processing and Control
Editorial: Institute of Electrical and Electronics Engineers
ISBN: 978-987-1648-44-3
Idioma: Inglés
Clasificación temática:

Resumen

An all-digital high-resolution symmetric pulse-width modulator based on a custom delay integrated circuit is presented. The topology uses two complementary trailing-edge PWMsignals from an FPGA to set the coarse adjustment of the symmetric duty-cycles, and the fine adjustment is provided by digitally-controlled delay lines with adjustable time resolution,implemented in a custom integrated circuit. More than 20 dB of reduction in the total harmonic distortion plus noise (THD+N) was measured with the proposed approach for a 1 kHz signal.
Palabras clave: PULSE-WIDTH MODULATION (PWM) , DELAY-LINE , CMOS INTEGRATED CIRCUITS , PROGRAMMABLE DELAY , FPGA
 
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Tamaño: 1.489Mb
Formato: PDF
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Licencia
info:eu-repo/semantics/restrictedAccess Excepto donde se diga explícitamente, este item se publica bajo la siguiente descripción: Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Unported (CC BY-NC-SA 2.5)
Identificadores
URI: http://hdl.handle.net/11336/234043
URL: https://ieeexplore.ieee.org/document/8882148
Colecciones
Eventos(IIIE)
Eventos de INST.DE INVEST.EN ING.ELECTRICA "A.DESAGES"
Citación
Implementation of a High-Resolution Symmetric PWM Based on Custom CMOS Delay Lines; XVIII Workshop on Information Processing and Control; Argentina; 2019; 1-6
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