Effects of clock jitter noise in the performance of digital filtering techniques for CCD readout

Abstract

This article provides insight into the effects of jitter induced noise in the pixel value when digital readout techniques are used for charge coupled devices (CCD). Available publications only focus in the CCD electronic noise component while this work analyzes the impact of jitter for readout schemes in which samples near and within the transition of the video signal between the pedestal level and charge level are used. This is the case when fast read outs are required or when optimal filtering techniques are used. The fast voltage swing of the video signal due to feed-through of the clocks in the aforementioned transition amplifies any timing error in the ADC sampling.