Comparison of the degradation characteristics of AlON/InGaAs and Al2O3/InGaAs stacks

In this paper, the degradation characteristics of MOS (Metal-Oxide-Semiconductor) stacks with Al2O3/AlON or Al2O3 only as dielectric layers on InGaAs were studied. The dielectric nitrides are proposed as possible passivation layers to prevent InGaAs oxidation. At negative bias, it has been found out that the main contribution to the overall degradation of the gate oxide is dominated by the generation of positive charge in the gate oxide. This effect is pronounced in MOS stacks with Al2O3/AlON as dielectric, where we think the positive charge is mainly generated in the AlON interlayer. At positive bias, the degradation is dominated by buildup of negative charge due to electron trapping in pre-existing or stress-induced traps. For stress biases where the leakage currents are low, the changes in the electrical characteristics are dominated by electron-trapping into traps located in energy levels in the upper part of the semiconductor gap. For stress biases with higher leakage current levels, the electron tra...


I. INTRODUCTION
InGaAs is an attractive candidate to be used as a channel material for the extension of CMOS (Complementary Metal-Oxide-Semiconductor) technology beyond Si due to its high electron mobility. [1][2][3] Lacking a good native oxide interface, a major challenge is the reduction of the density of interface states (D it ) at the semiconductor interface. 3,4 High D it values lead to inefficient Fermi level response, degrade the control of charge concentration in the channel, decrease the subthreshold slopes, and reduce the drive current of metal-oxide-semiconductor field effect transistors (MOSFETs). 5 High D it values are manifested in the capacitance-voltage (C-V) measurements as a hump at the weak inversion regime, a phenomenon that is almost always observed in InGaAsbased gate stacks at room temperature. [6][7][8][9] Krylov et al. have shown that an ammonia (NH 4 OH) pretreatment of the InGaAs surface improved the C-V characteristics of alumina-based MOS capacitors, and reduced the mid-gap D it . An X-ray photoelectron spectroscopy (XPS) study revealed that the treatment with NH 4 OH suppressed Ga-O bonds development only after annealing in N 2 for 30 min at 400 C. 10 It should be noted that the improvements in Dit have been achieved to such levels that the multi-frequency C-V response associated with genuine surface inversion has been achieved. [11][12][13] Despite the wide literature available about the good interface passivation and excellent device performance obtained with this approach, very few reliability studies of this MOS stack have been reported. 1,2 We have shown in Ref. 14 that the degradation of such capacitors is strongly affected by the oxide-semiconductor surface treatment. Surface treatment with NH 4 OH shows a better quality of the interface in terms of interface states; 10 however, it contributes to generation of charge on the dielectric layer. The charge generation is mainly due to the interface contribution, since the accumulation of trapped charge is accompanied by the generation of interface states. 14 The physical origin of the interface contribution can be understood in terms of the dissociation of the bonds at the interface (i.e., depassivation of the interface). 14,15 Therefore, since the suppression of the Ga-O bonds by the treatment with NH 4 OH only occurs after the annealing in N 2 , it opens the question about the role of N in the generation of defects/charge in the gate oxide.
Although it is well known that in standard Si/SiON stacks the addition of N to the SiO 2 gate oxide has an adverse effect on reliability, [16][17][18] there is no information about the role of N in the degradation of high-k dielectric/InGaAs stacks. It is clear that more information is needed to describe and model the mechanisms responsible for the degradation of high-k dielectric/InGaAs stacks.
In this work, the analysis of the degradation characteristics of metal gate (MG)/high-k dielectric/InGaAs stacks with Al 2 O 3 /AlON in comparison to Al 2 O 3 only gate dielectrics is performed under constant voltage stresses (CVS).The addition of N is not applied to the InGaAs interface by NH 3 treatment as in Ref. 10, but rather by creating with ALD (atomic layer deposition) an N-enriched AlOx inner layer; NH 4 OH was used as a chemical passivation step for both samples prior to the ALD. In the first part of the manuscript, the influence of the AlON interlayer on the electrical characteristics is analyzed, while the second part is focused on the study of a) Author to whom correspondence should be addressed. Electronic mail: felix.palumbo@conicet.gov.ar. Tel.: þ54-11-6772-7128. the dynamics of degradation of the flat band voltage (V FB ) and the generation of defects at interfaces of the stack.

II. EXPERIMENTAL
An n-type Sn-doped In 0.53 Ga 0.47 As layer (7 Â 10 16 cm À3 ) 500 nm thick was grown by metal-organic molecular beam epitaxy (MOMBE) on an n-type InP substrate. Before ALD of the dielectric stacks, the samples were cleaned in acetone, methanol, and propanol, rinsed in de-ionized water (DI), dipped into a diluted H 2 SO 4 solution for 30 s, dipped into DI water, and treated with NH 4 OH 36% solution for 1 min. The samples were introduced into the ALD chamber within less than 3 min after the pre-deposition treatment. This procedure results in a relatively low density of interface states. 10 Two different gate dielectric stack were deposited by ALD at 270 C-Al 2 O 3 (20 nm) and Al 2 O 3 (10 nm)/AlO x N y (10 nm). The deposition precursors of Al 2 O 3 were trimethylaluminium (TMA) and H 2 O, while tetrakis-dimethylaminoaluminium and NH 3 served for the deposition of AlO x N x . The thickness of the samples was confirmed by ellipsometry. We note that both gate stacks have a similar physical thickness of the dielectric layer. The gate electrode, Au (200 nm)/Ti(%2 nm) was deposited by electron beam deposition and patterned by the lift-off technique. The area of all devices is 4 Â 10 À4 cm 2 . The samples were annealed in N 2 at 400 C for 5 min. We note that both kinds of gate stacks have the same metal/ dielectric interface while the dielectric/InGaAs interface differs by the nitrogen content in the dielectric.
C-V measurements were carried out at different frequencies using an Agilent 4285A LCR meter. Current-Voltage (I-V) and CVS measurements were performed using an Agilent 4155C parameter analyzer. During CVS, the stress was periodically interrupted for C-V measurements to track the degradation of the device parameters such as V FB . For each stress condition, a dozen of devices were measured. To avoid recovery-related artifacts, we kept constant values of the delay time between the C-V measurements and the CVS pulses. The calculation of V FB was performed by the recently introduced inflection point technique. 19

III. RESULTS
A. Influence of the AlON interlayer Figure 1 shows typical C-V hysteresis curves at 500 KHz of the two sets: set A (Al 2 O 3 /AlON) and set B (Al 2 O 3 ). The C-V hysteresis measurement was done in a retrace mode, where the voltage was swept from inversion to accumulation and back to inversion (see arrow 1 in Figure 1). It should be noted that both C-V curves reach the same level at inversion if the voltage limit is large enough. While in strong accumulation if the voltage limit is large enough set A (Al 2 O 3 /AlON) reaches a higher value of capacitance that might be explained by an increase of the k value for the AlON interlayer. 20 By comparing the C-V curves in Figure 1, we observe similarity in the C-V hysteresis measured at flat band (DV FB Hysteresis % 0.055 V for both sets), but differences in the C-V stretch out showing that the main difference between both sets of samples is related to the density of interface states, and not to the charged defects close to the oxide/ InGaAs interface, namely, border traps. 21,22 The MOS stack with the AlON/InGaAs interface (set A) shows a reduction in the C-V stretch out, which is a clear indication of a lower density of interface states. This is also consistent with the reduction of the frequency dispersion of the C-V at negative bias ( Figure 2), defined in the literature as "weak inversion hump," which is attributed to oxide/InGaAs interface states. 10 These results suggest, in agreement with recent papers, 20,23 that the dielectric nitrides are possible passivation layers to prevent InGaAs oxidation. It might be attributed to a smaller extent of out-diffusion of Ga and As atoms from the substrate into the high-k dielectric layer associated with the blocking role of AlON. 20 Another relevant feature of Figure 1 is the difference between both sets in the flat band voltage (V FB ). The larger positive value of V FB for set A (Al 2 O 3 /AlON) can be explained by the characteristics of the AlON interlayer. Choi et al. have shown that the incorporation of nitrogen in high-k dielectrics during ALD deposition on semiconductors such as GaN, Si, and III-As acts as a source of negative fixed charge. 24 On the other hand, regarding the density of interface states, it was reported that the incorporation of nitrogen may be also effective in alleviating the problem of native interface defects. 24 Therefore, the incorporation of N into Al 2 O 3 to form AlON explains both the increase of V FB and the decrease of interface states as observed in Figure 1.
Finally, it is worth to note that the frequency dispersion in strong accumulation is similar in sets A and B ( Figure 2). Although it is reported that AlON oxide layers show less dispersion in frequency at strong accumulation, 20 it may occur that the variations are not significant to be measured since the oxide thicknesses of the samples in our study are relatively thick (20 nm). Figure 3 shows the current-voltage (I-V) characteristics of both sets, where we observe large differences at positive and negative polarities. Since the physical thickness of the dielectrics is the same for both sets of samples, and the metal/dielectric barrier is the same, the main reason of such differences must be related to the high-k/InGaAs barrier. 25 Based on the characteristics found in literature, it is reasonable to assume that the AlON/InGaAs barrier is smaller compared to the Al 2 O 3 /InGaAs barrier due to a reduction of the oxide band gap of AlON. 23,26 Figure 4 shows the general trend of the absolute values of V FB after CVS on both polarities for sets A and B. The samples were stressed at similar V G -V FB values ranging from À2.4 V to À5.4 V ( Fig. 4(a)), and from þ2.1 V to þ4.6 V ( Fig. 4 (b)). It is observed that the shift of abs (V FB ) for set A (Al 2 O 3 /AlON) dominates at high stress values. Hence, even though the MOS stack with AlON/InGaAs interface (set A) shows lower density of interface states (i.e., smaller C-V stretch out), it contributes with much more charge than the Al 2 O 3 /InGaAs stack (set B) after CVS pulses at high voltages.
At this point it is particularly relevant to understand the origin of such observations. Although the larger shifts of the electrical characterizations of the set A (Al 2 O 3 /AlON) could be associated with higher leakage currents levels, 27,28 there is evidence in the literature that trapping 29 and/or depassivation of the high-k/InGaAs interface 14,15 may also contribute to the degradation of the MOS stack.

B. Electrical stress at negative polarity
To clarify the physical origin of the changes generated due to stress at negative polarity, V FB was studied as function of the stress voltage. Figure 5 shows the shift in V FB as function of the stress voltage for CVS pulses of short  (Fig. 4(a)), and from þ2.1 V to þ4.6 V ( Fig. 4(b)). duration (%1 s). V FB was measured from consecutive C-V curves at 500 KHz while decreasing the minimal DC bias point in inversion (namely, the stress voltage in Figure 5), and with the same maximal DC bias point in accumulation. Since the recovery of trapped charge for the InGaAs/Al 2 O 3 MOS system can be fast, 29 special attention was taken to keep constant and small (100 ms) the values of the delay time between measurements. This methodology extensively used to stress MOS stacks 29-31 allows CVS pulses of short duration, reducing the percentage of trapped charge removed during the delay time, and avoiding recovery-related artifacts. 30 Figure 5 illustrates the effect of the minimal DC bias in inversion (marked as stress voltage in Fig. 5) on the shift of V FB for sets A (Al 2 O 3 /AlON) and B (Al 2 O 3 ). Similar shifts of V FB for stress voltages up to À5 V are observed for both sets. For more negative stress voltages, set A (Al 2 O 3 /AlON) shows a significant decrease in V FB . By comparing the results of Figure 5 with the I-V curves of Figure 3, it is clear that charge build-up due to higher injection current during the stress is not the reason for the decrease in V FB of set A (Al 2 O 3 /AlON). The increase in current in the I-V curve (which occurs around À9 V) is not related to the onset point (%À5 V) of the decrease of V FB of set A (Al 2 O 3 /AlON). It should be emphasized that these results are independent of the duration of the CVS pulse. As observed in Figure 4, a similar behavior is observed in longer CVS pulses. Figure 6 shows the V FB values calculated from the C-V hysteresis curves in the retrace mode (where the voltage was swept from inversion to accumulation and then back to inversion as exhibited in Fig. 1) after consecutives CVS pulses. The V FB values marked by close symbols were measured with the voltage swept from inversion to accumulation, while the V FB values marked by open symbols were measured from the C-V curve when the voltage was swept back to inversion. Therefore, the difference between both curves is the hysteresis at flat band (DV FB hys ). Figures 6(a) and 6(b) show the V FB values using this methodology for set A(Al 2 O 3 /AlON) and B (Al 2 O 3 ), respectively, as function of the time during CVS pulses followed by an annealing at room temperature (27 C) without bias on the gate contact. As result of the stress pulses, the C-V curves shift towards negative bias indicating accumulation of positive charge in the gate oxide. It should be noted that the current level for the bias condition used in this figure (V G -V FB ¼ À5.4 V) is of the order of pA for both sets of samples (see Figure 3) to avoid charge build-up due to higher leakage currents.
We observe that even though the shift in V FB is much larger for set A (Al 2 O 3 /AlON), the magnitude of the hysteresis after the stress is similar for both samples. This observation suggests that the stress-induced charge (responsible for the shift in V FB ) is mainly related to the volume of the AlON layer, since the defects that contribute to the C-V hysteresis are close to the oxide/InGaAs interface. 14,21,22,31 It should be pointed out that for both sets of samples the shift in V FB includes an additional component of degradation. This is observed in Figure 6 by the fact that the C-V hysteresis and the conductance peak (results not shown here) increases significantly after the stress in both sets of samples. It should be noted that the charge trapping responsible for the C-V hysteresis is taking place primarily in the interfacial oxide transition layer between InGaAs and the ALD deposited oxide. 31 On the other hand, the measurements by the conductance method correspond to fast D it states around mid-gap. 5 Finally, we also observe recovery of the flat band voltage during the annealing at RT without bias on the gate contact. Although the recovery of the V FB after CVS is not the scope of this work, the magnitude of this effect is consistent with earlier reports. 29,30 The comparison of the degradation characteristics at negative bias between set A (Al 2 O 3 /AlON) and set B (Al 2 O 3 ) shows that the degradation is significantly enhanced when nitrogen (N) is added into the gate dielectric. We find that the main mechanism of degradation is not related to the high levels of leakage current through the gate oxide, but rather the volume of the AlON interlayer plays a major role in the overall degradation. At stress with a negative bias, we observe two components of positive charge build-up. One component, which is present in both sets of samples, is associated with the generation of defects near the oxide/InGaAs interface due to the increase of the C-V hysteresis. The other component occurs only when the AlON interlayer is present. In this case, the generation of positive charge is independent of the C-V hysteresis indicating that the incorporation of nitrogen into the dielectric is the main reason of the charge build-up.
These results clearly show that the improvement of the dielectric/InGaAs interface by an AlON interlayer increases at the same time the buildup of oxide charges under CVS with negative bias. Therefore, further studies about the degradation characteristics in terms of the nitrogen content are needed to find the proper concentration that can improve the oxide/InGaAs performance without affecting the reliability of the stack.

C. Electrical stress at positive polarity
At positive bias the CVS experiments show a different behavior. Figure 7 shows the shift of V FB as function of the stress voltage of CVS pulses of short duration using the same methodology of Figure 5. In this case, the V FB values were measured from consecutive C-V curves where the same starting DC bias point in inversion was used, with an increasing maximal DC bias point in accumulation, marked as the stress voltage in Figure 7. We observe two regions as function of the stress voltage. At low voltages (<þ4.5 V) both MOS stacks show a similar dynamics with no differences in the V FB values, while at higher voltages (>þ4.5 V), set A (Al 2 O 3 /AlON) shows a significant increase of V FB . Contrary to the previous case of Figure 5, the onset of this variation is related to the increase of the current in the I-V characteristics in Figure 3, suggesting that it is a consequence of higher injection currents during the CVS experiment. 27,28 Figure 8 shows the V FB values measured from the C-V hysteresis curves with the same methodology of Figure 6. The V FB values marked by close symbols were measured with the voltage swept from inversion to accumulation, while the V FB values marked by open symbols were measured from the C-V curve when the voltage was swept back to inversion. Figures 8(a) and 8(b) show typical results for both sets of samples after CVS pulses at V G -V FB ¼ þ2.1 V, where the leakage current is of the order of pA. Figures 8(c) and 8(d) show similar results after CVS pulses but for V G -V FB values in the high voltage range (>þ4.5 V), where the leakage current level is not equal for both sets. The current level for the set A (Al 2 O 3 /AlON) is two orders of magnitude higher than the current level of set B (Al 2 O 3 ). It can be observed that in the regime of low voltages (Figures 8(a) and 8(b)) the dynamic of the V FB shift is similar for both sets, showing no change in the magnitude of the shift (%0.05 V), in the hysteresis (%0.05 V), and in the conductance peak (see insets of Figures 8(a) and 8(b)). It is worth to note that the C-V hysteresis and the conductance peak are related to the generation of defects near the oxide/InGaAs interface and fast interface traps around the mid-gap, respectively. On the other hand, in the regime of higher voltages (Figures 8(c) and 8(d)), we observe large differences in the dynamics of the V FB shift as function of time, which are associated with the increase of the leakage current. Note that the set A (Al 2 O 3 /AlON) shows a significant increase of V FB , and of the conductance peak (see inset of Figure 8(c)) indicating generation of defects during the CVS. The overall analysis of the dynamics of the V FB shows that the buildup of negative charge (i.e., V FB shift towards positive bias) is similar for both sets of samples as long as the leakage current level remains low.
This analysis can be extended by studying the particular features of the C-V curves after the stress pulses.  Figures 10(a) and 10(b) show a similar comparative analysis between both sets, but in the high voltage regime (V G -V FB ¼ þ4.6 V). In this case, we observe large differences between the C-V curves, as expected from Figure 8. Figure 10(a) shows, for set A (Al 2 O 3 /AlON), a translation of the C-V curve towards positive bias after the CVS, indicating accumulation of negative charge in the gate oxide, while Figure 10(b) shows, for set B (Al 2 O 3 ), a different behavior. After the CVS pulse, we observe a shift towards positive bias only of the upper part of the C-V curve, showing similar features to those observed at low voltages (see Figure 9). It should be noted that even though the bias conditions in Figure 10 are similar for both sets of samples, the leakage current levels are not the same, showing a difference of more than two orders of magnitude (see Figure 3).
Based on these observations, we believe that the buildup of negative charge under positive bias could be caused by electron trapping. At low voltages, with very low leakage currents, the shift of V FB reflects the carrier/defect energy alignment in the MOS stack as was suggested in our previous paper. 32 The changes in the electrical characteristics are dominated by electron trapping into traps located in the oxide, at energy levels aligned with the upper part of the InGaAs gap. We believe that electron trapping is the main mechanism due to the absence of any modification of the C-V hysteresis and the conductance peak after the CVS.
Regarding the location of the traps, the similar features of the C-V curves for both sets (the equal difference between the onset point V O with respect to V FB in the C-V curves; V FB -V O ¼ 0.15 V) indicate that the onset point for the distribution does not depend on the dielectric layer, in agreement with our previous paper. 32 In this regime, as long as the leakage current remains low, we observe similar features of the C-V and of the dynamics of V FB as function of the time under CVS pulses for both set of samples.
At high voltages, when the leakage currents are high, it is clear that the negative charge build up (i.e., C-V shift towards positive bias) is accompanied by generation of defects due to the higher leakage current levels, suggesting that electron trapping into defects generated by such higher injection current may also be responsible for the shift of V FB towards positive bias.

IV. SUMMARY
In this paper, the influence of the addition of N to alumina-based gate oxide was studied by the comparison of the degradation characteristics of MOS stacks with Al 2 O 3 / AlON and Al 2 O 3 as dielectric layers. It has been observed that the high-k/InGaAs stacks behave differently under positive and negative stress bias. Under negative stress bias, the degradation is dominated by the generation of positive charge in the gate oxide, and the accumulated charge is larger for MOS stacks with Al 2 O 3 /AlON as dielectric. The physical reason for such a difference lies in the origin of the generated charge that shifts the V FB . It has been demonstrated that the main contribution to the overall degradation of the gate oxide occurs in the volume of the AlON interlayer, resembling the situation of standard SiON/Si stacks, where the addition of N to the SiO 2 gate oxide has a serious adverse effect on reliability.
Under positive stress bias, the degradation is dominated by buildup of negative charge due to electron trapping in preexisting or stress-induced traps. For stress bias with low leakage currents, the changes of the electrical characteristics are dominated by electron-trapping into traps located in energy levels in the upper part of the semiconductor gap. For stress bias corresponding to higher leakage current levels, an additional component contributes to the degradation of the MOS stacks. In this regime, the electron trapping occurs in stressinduced traps, increasing thus the shift of V FB towards positive bias.
The analysis of the electrical degradation is of utmost importance since InGaAs is the front runner candidate for n-type channels MOSFET. The results presented in this paper contribute to a better understanding of the limiting factors of the reliability of Al 2 O 3 /InGaAs stacks. The overall results clearly show that the improvement of the high-k dielectric/InGaAs interface does not necessarily mean an increase of the reliability of the MOS stack. In the case of N addition to Al 2 O 3 , the D it improvement is followed by a compromise in the capacitor reliability.