Characteristics of stress-induced defects under positive bias in high-k/InGaAs stacks

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InGaAs is an attractive candidate to be used as a channel material beyond Si thanks to its high electron mobility.Lacking a good native oxide interface, a major challenge in using it is the characterization and the understanding of the various defects components that affect the high-k dielectric/ InGaAs performance and long term reliability. 1 One of the most common approaches for defect characterization is the capacitance-voltage (C-V) measurement over a wide range of frequencies. 24][5] In addition, in the strong accumulation regime, defects produce a frequency dispersion that cannot be explained by conventional interface states whose time constant in such bias regions is far shorter than the period of typical measurements frequencies (1 KHz-1 MHz). 5,6Some authors attributed this dispersion to defects located within the oxide near the oxide/InGaAs interface (referred in the literature as "border traps"), which can communicate with the conduction and valence bands of the InGaAs by tunneling. 7owever, recent results show a temperature dependence of the frequency dispersion in accumulation induced by the so called "border traps." 8,9On the other hand, some authors attribute the frequency dispersion in strong accumulation to a disordered interface layer due to substrate oxidation. 10,11uch observations pose a question on the real nature of the defects responsible for the dispersion of C-V in strong accumulation.In this work, we study the generation of defects in strong accumulation by constant voltage stresses as function of the dielectric deposition process (i.e., quality of the interface) and the type of the dielectric layer used.
Different sets were used on n-type InGaAs substrates epitaxially grown on InP wafers.In set A, a pre-dielectric deposition treatment (PDT) was performed by a 36% NH 4 OH solution.Then a 9 nm-Al 2 O 3 layer (the most common dielectric for InGaAs) was prepared by atomic-layerdeposition (ALD).In set B, a 9 nm-Al 2 O 3 film was deposited by the same ALD process but without the NH 4 OH PDT.For set C, a different dielectric was used-following the PDT a 10 nm-HfO 2 layer was deposited by ALD.In all sets, the area of the devices was 1.1 Â 10 À4 cm 2 , and the gate metallization consisted of Ti(1 nm)/Au(200 nm) deposition.In all cases, the metal deposition was followed by annealing at 400 C in N 2 flow for 30 min.Description of the samples is summarized in Table I.
Capacitance-Voltage (C-V) measurements were carried out at different frequencies from inversion to accumulation.During constant voltage stress (CVS), the stress was periodically interrupted to measure the V FB by the inflection point technique. 12In order to avoid recovery-related artifacts, we kept constant values of the delay time between the C-V measurements and the CVS pulses.It is worth to note that in this work the CVS experiments were performed at room temperature (27 C) and at 125 C, while the C-V measurements between CVS pulses were performed at room temperature.
Figures 1(a) and 1(b) show typical consecutive C-V curves for set A after CVS pulses at negative bias (À4.8 V) and positive bias (þ4 V), respectively, with an accumulated stress time of 10 min in both cases.Although the degradation at negative bias is not a topic of this paper, it is clear from Figure 1 that positive and negative stress bias behave differently, in agreement with previous works. 13,14At negative CVS, the whole set of C-V curves shifts towards negative bias indicating accumulation of positive charge (Fig. 1(a)), while at positive CVS, the C-V curves shift towards positive bias indicating accumulation of negative charge (Fig. 1(b)).The main feature of the experiment under positive CVS on which we focus is the non-uniform shift of the C-V curves showing that only the upper part of the C-V is affected by the positive stress.This feature is characterized by an onset point, marked as V O in Fig. 1(b), from which the shift of the C-V curves is observed.
In order to explore the origin of such a particular feature, we decided to study the influence of the oxide/semiconductor interface on this phenomenon.CVS experiments were performed on samples of set A (treated with NH 4 OH) and of set B (without treatment).Such differences are clearly observed in the typical multi-frequency C-V curves of the two sets given in Figure 2. Set A, (Fig. 2(a)), shows a relatively small increase of the capacitance in the inversion regime; while in set B, (Fig. 2(b)), the capacitance is increased significantly in this regime.As reported in our previous works, the area under the C-V "weak inversion hump" (Q hump ) is related to the density of interface states. 5,15In our case, the area Q hump under the C-V measured at 100 kHz shows a reduction from 4.7 Â 10 À7 C/cm 2 for set B to 2.5 Â 10 À7 C/cm 2 for set A, indicating the efficiency of the NH 4 OH treatment for reducing the density of interface states for Al 2 O 3 /InGaAs gate stacks.Moreover, it is observed that the dispersion with frequency of the accumulation capacitance is small and similar for both sets of samples, indicating no influence of the NH 4 OH treatment on the traps responsible for the dispersion in accumulation, mentioned in the literature as "border traps." 16,17The latter observation together with a similar C-V hysteresis at flat band condition for both sets (DV Hyst FB ¼ 0.10 V and DV Hyst FB ¼ 0.09 V for sets A and B, respectively) indicate a similar density of this kind of traps. 18igure 3 shows a comparative analysis of consecutive C-V curves after CVS at þ4 V with an accumulated stress time of 10 min for both sets.We recall that set A is with a lower density of interface states than set B, but both have similar density of border traps.In both cases, there is a shift towards positive bias of the upper part of the C-V curves with a similar onset point V O .An interesting aspect is the equal difference between the onset point V O with respect to V FB in the C-V curves (V FB À V O ¼ 0.15 V) for both samples.It indicates that the Fermi level position at the oxide/ semiconductor interface for the V O condition is similar in both cases, hence independent of the characteristics of the oxide/semiconductor interface.
To clarify the influence of the dielectric layer, additional measurements were performed on a similar MOS stack using a different dielectric layer (set C). Figure 4 shows consecutive C-V curves after CVS pulses at positive bias (þ3 V) with an accumulated stress time of 10 min for the case of MG/HfO 2 /n-InGaAs.For a better description, we included only the first and the last C-V curve of the consecutive C-V series.A shift of the C-V curves towards positive bias is observed only on the upper part of the C-V curve with a similar onset point.This indicates an accumulation of negative charge.It is worth that similarly to the other cases, the difference between the onset point V O with respect to V FB in the C-V curves is V FB À V O ¼ 0.15 V.The occurrence of this particular feature during the CVS at positive bias is independent of the quality of the interface and of the type of dielectric layer.It is a clear indication that the accumulation of negative charge is only related to characteristics of the substrate (InGaAs).
It is important to note that the occurrence of such a particular feature is not an artifact and is observed in a large range of bias in the CVS experiments and frequencies in the C-V curves.The observation of the onset point is independent of the frequency of the C-V curves in the range of 1 MHz-100 KHz.At low frequencies (near 10 KHz), the influence of the interface states in the C-V curves through the "weak inversion hump" makes it difficult to identify the onset point, V O .Therefore, most of the analyses reported here are based on C-V curves measured at 500 KHz to avoid influence of interface states. 2 Moreover, the occurrence of the onset point, V O , was verified over a large range of bias during the CVS (from þ3 V to þ5 V) showing the same behavior until a breakdown event, indicating that V O is also independent of the stress time.
Figure 5 shows the typical C-V curves of set A after CVS pulses at high temperature.After the first CVS pulse at þ3 V for 10 min at 125 C, the C-V curve (curve 1) shows a shift of the upper part towards positive bias, however, the lower part of the C-V curve shifts towards negative bias increasing the stretch-out.After the second CVS pulse at þ3 V for 10 min at 125 C, the C-V curve (curve 2) shifts towards positive bias without an additional stretch-out indicating accumulation of negative fixed charge, likely due to electron trapping in the stress-induced defects.
Contrary to what is observed with CVS at room temperature, the conductance also increases significantly in this case.The inset in Figure 5 shows an increase of the conductance peak after the first CVS pulse at 125 C, while the magnitude of the peak after CVS at RT remains similar to the fresh device.Therefore, the overall results show that the degradation under positive bias consists of two contributions depending on the temperature.At room temperature, the changes of the electrical characterizations are dominated by electron-trapping into traps located in energy levels in the upper part of the semiconductor gap.We believe that electron trapping is the main mechanism due to the absence of any modification of the hysteresis (Table II) and the conductance peak during the CVS (inset in Fig. 5).Regarding the distribution in energy, the particular features of the C-V curves after the CVS show an onset point for the distribution that does not depend on neither the quality of the oxidesemiconductor interface (based on the comparison of sets A and B), nor on the dielectric layer (comparison of sets A and C).Since the onset point maintains a constant difference FIG. 3. Consecutive C-V curves at 500 KHz after CVS at þ4 V at room temperature with an accumulated stress time of 10 min for sets A and B (with and without NH 4 OH treatment, respectively).An interesting aspect is the equal difference between the onset point V O with respect to V FB in the C-V curves (V FB À V O ¼ 0 .15V) for both samples.FIG. 4. Consecutive C-V curves at 500 KHz after CVS at þ3 V at room temperature with an accumulated stress time of 10 min.It is worth to note that also in this case, the difference between the onset point V O with respect to V FB in the C-V curves is V FB À V O ¼ 0 .15V. with respect to V FB (V FB À V O ¼ 0.15 V), this point may correspond to the position of the Fermi level in the bandgap of the semiconductor near the midgap condition.This onset point would agree well with the calculated as anti-site (As Ga ) defect level. 19t a high temperature, a different behavior is found for CVS, giving indication that a new component contributes to the degradation of the MOS stack.Contrary to the previous case, the C-V curves show an increase of the stretchout, the hysteresis, and the conductance peak, indicating that the generation of defects at the oxide-semiconductor interface contributes to the degradation.In our previous work, we have reported that the V FB does not show a temperature dependence after CVS at positive bias, 5 therefore, one may conclude that the increase of the stretch-out is generated by defects that only contribute when the V G range is in the lower part of the C-V (i.e., in the lower part of the semiconductor gap).However, the increase of the hysteresis in the same CVS condition (Table II) is a clear indication that the generation of border traps also contributes to the degradation.This increase of the density of border traps does not result in an increase of the frequency dispersion in accumulation (results not shown).It may occur since the oxide thickness of the samples is relatively thick (9 nm), and hence the capacitance contribution of such defects is not significant to be measured.
The non-uniformity of generation of defects after CVS is in agreement with recent results.Jiao et al. 20 showed on Al 2 O 3 /InGaAs that the stress-induced trap density under positive bias could be understood in terms of acceptor and donor traps in the upper and lower part of the gap, respectively.
Our results show that border traps and interface stated are the main contributors in the upper and lower part of the semiconductor bandgap, respectively.Based on the features of the stressed C-V curves, it is possible to estimate the onset point of the distribution of border traps near the midgap condition, while comparing different MOS stacks with different dielectrics it is reasonable to suggest that the border traps are strongly related to the characteristics of the InGaAs.Regarding the generation of interface estates, the main characteristic is their thermal activation during CVS experiments.

FIG. 1 .
FIG. 1. Consecutive C-V curves at 500 KHz for set A (treated with NH 4 OH) at room temperature after (a) CVS at À4.8 V, and (b) CVS at þ4 V.Both cases correspond to an accumulation time of CVS of 10 min.The main feature is the non-uniform shift of the C-V curves showing that only the upper part of the C-V is affected by the positive stress.

FIG. 5 .
FIG.5.Consecutive C-V curves at 500 KHz at room temperature after CVS pulses at high temperature on set A (treated with NH 4 OH).Curves 1 and 2 correspond to pulses of þ3 V at 125 C for 10 min.The inset shows the normalized parallel conductance peak after stress at þ3 V at room (27 C) and high temperature (125 C).It is worth to note that the measurements between CVS pulses were performed at room temperature.

TABLE I .
Description of samples studied.

TABLE II .
Description of C-V hysteresis.